Recent benchmarks of Linux's proposed cache aware scheduling patches demonstrate significant performance improvements on AMD's EPYC Turin processors. The patches, developed by Intel engineers, aim to optimize task placement for better cache locality on multi-cache CPUs. Testing on a dual EPYC 9965 setup revealed promising results for heterogeneous server workloads.
Over the past several months, Intel Linux kernel engineers have been developing cache aware scheduling to enhance performance on modern CPUs with multiple cache levels. This approach aggregates tasks likely to share resources into the same cache domain, improving cache locality and efficiency.
The patches, which have moved beyond the request for comments stage, were updated earlier in October. Initial reports highlighted a 44% time reduction in one benchmark, along with improvements on platforms like Intel Xeon Sapphire Rapids, AMD EPYC Milan, and AMD EPYC Genoa.
For this evaluation, tests were conducted on the Linux 6.17 kernel using AMD's flagship EPYC 9005 "Turin" series, specifically the 192-core EPYC 9965 processors. The setup featured a dual-socket AMD Volcano server with 192 cores and 384 threads per socket, equipped with 384MB of L3 cache.
Comparisons were made between a stock Linux 6.17 kernel and the same kernel modified with the 11 October cache aware scheduling patches enabled. Tunables for cache aware scheduling, accessible via sysfs, were left at their default settings during testing.
While cache aware scheduling offers benefits for many workloads, it is not universally advantageous. A specific patch disables it for processes with thread counts exceeding the physical cores in the last-level cache (LLC) to prevent cache contention. The feature shows particular promise for typical heterogeneous Linux server environments that do not fully saturate the CPU.