IBM has developed a prototype computer chip that packs nearly 100 billion transistors into a fingernail-sized device. The 10 by 15 millimetre chip uses a new three-dimensional layering technique to achieve record density.
The company claims the chip will deliver 70 per cent higher energy efficiency and 50 per cent higher performance than current leading models. It is expected to reach commercial devices within the next decade.
The technology involves bonding two layers of silicon circuitry to enable scaling in the vertical Z direction for the first time. IBM spent 15 years developing the process, which it describes as building on its earlier 2-nanometre chip announced in 2021.
The prototype is labelled as 0.7-nanometre technology, though this refers to a roadmap designation rather than literal component size. Individual circuit parts measure just 15 silicon atoms thick.
Industry experts note that integrating the untested second layer into mass production on 300-millimetre wafers will present significant manufacturing challenges.